This invention relates to a flip-chip integrated circuit assembly, and processes for assembling the integrated circuit assembly using flip-chip techniques.
In recent years, technologies have emerged which can provide high density electrical interconnections between an integrated circuit (IC) chip and a substrate to form IC assemblies, otherwise known as IC packages. These technologies for forming electrical connections between an IC chip and a substrate are commonly known as wire bonding, tape-automatic bonding (TAB) and solder flip-chip bonding. Although, all these bonding techniques can be used to form high density electrical interconnections, the use of one particular technique over another is typically dictated by the desired number and spacing of the electrical connections on the IC chip and the substrate, as well as the permissible cost for assembling the IC package.
In a comparison of these three techniques, wire bonding is the most common technique for electrically connecting an IC chip to a substrate. This is due to that fact that this technique provides the maximum number of chip connections with the lowest cost per connection. A disadvantage of wire bonding is that inductance present in the wires used in connecting the IC chip to the substrate degrades the electrical performance of the assembled IC package. Moreover, since the wires connect perimeter connections of the IC chip to contacts on the substrate in areas not occupied by the IC chip, wire bonding electrical interconnects require a relatively large surface area of the substrate. Lastly, since wire bonding requires each connection between the IC chip and the substrate to be made one at a time, the process of electrically interconnecting an IC chip to a substrate using the wire bonding technique is somewhat time consuming.
TAB bonding permits a higher density of electrical interconnects when compared to wire bonding. However, TAB bonding is more expensive than wire bonding because TAB bonding requires special tooling for each different IC chip design. Also, like wire bonding, TAB bonding requires perimeter connections and therefore a relatively large surface area of the substrate to accomplish the IC chip and substrate electrical interconnect. Moreover, like wire bonding, undesirable inductance as a result of TAB bonding degrades the electrical performance of the IC chip circuitry.
Flip-chip bonding is achieved by providing an IC chip with an area array of solder wettable contact pads which comprise the signal terminals on the chip. A matching footprint of solder wettable contact pads are provided on the substrate. Before assembly onto the substrate, solder bumps are deposited on the metal pads of the chip and/or the substrate. The chip is then placed upside down on the upper surface of the substrate such that the metal pads (solder bumps) of the chip are in alignment with the metal pads (solder bumps) of the substrate. All connections between the chip and the substrate are then made simultaneously by heating the solder bumps to a reflow temperature at which the solder flows and an electrically conductive joint is formed between the contact pads of the IC chip and the substrate.
When compared to wire bonding and TAB bonding, flip-chip bonding of an IC chip to a substrate provides the advantage of requiring less surface area on the substrate, and thereby facilitates high-density interconnections commonly required in IC assemblies. Since the interconnections between the substrate and the IC chip in flip-chip bonding are short, well controlled electrical characteristics are provided, and undesirable inductance that can degrade the electrical performance of the IC chip circuitry is minimized. In other words, high speed signals are thus propagated in and through the packaged integrated circuits with minimum delay and distortion.
There is a need for improved integrated circuit assemblies. In particular there is a need for an improved integrated circuit assembly that can be assembled using flip-chip bonding techniques to achieve a packaged integrated circuit having low interconnect capacitance, thereby improving signal speed and eliminating some need for off chip driver cells. The improved integrated circuit assembly should provide these features while being amenable to high volume low defect manufacturing.
One embodiment of the present invention is an integrated circuit package that includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites electrically connected to the second array of interconnection sites of the package substrate. A second integrated circuit die has a first surface including an array of interconnection sites electrically connected to the first array of interconnection sites of the package substrate. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.